Chip-to-chip interconnect

The links that let several accelerators share work. Fast dedicated links let a group of chips act like one big chip; slower general-purpose links make them wait.

Layer 2 · Compute Hardware · Build and run time · reviewed 2026-10-30

Read first: GPUs & AI accelerators, Memory & bandwidth (HBM).

D1 · StoryFor young children and total beginners

Two chips share one model. Guess what happens if their link is slow.

Big AI models are often too large for one chip, so several chips share the work.

They must keep passing notes to each other. If the note-passing is slow, the chips sit waiting instead of working.

Two chips sharing one model keep passing notes

Chip A: works on its half
The link: carries notes between chips
Chip B: works on its half

Like: Pupils sharing one big puzzle, passing pieces across the table.

D2 · PictureFor curious beginners

A model can be split across chips in two main ways. Splitting by layers sends each chip a run of layers, and only a small bundle of results crosses between them per token. Splitting inside each layer (tensor parallelism) makes every chip do part of every layer, so they swap results many times per token.

General-purpose links such as PCIe connect a GPU to the rest of the computer and are fine for the first kind of split. Dedicated chip-to-chip links (NVLink-style, or open standards such as UALink) are much faster and can join many accelerators into one shared domain, which the second kind of split needs.

Beyond one box, network fabrics join many such groups into the clusters of the layer above.

Like: Passing notes across the table versus everyone writing on one shared whiteboard.
Where it breaks: Note-passing slows a little with each extra pupil. With chips, a slow link can make adding a second chip barely faster, or even slower, because every layer has to wait for the swap.

D5 · FrontierFor experts

D2 splits a model across chips by layers or within layers. The hard parts are how many chips one fast domain can hold, over what medium, and whose standard it uses.

Domain size. Splitting inside layers needs the fastest links. Training a trillion-parameter model on 3,072 GPUs reached 52% of peak only by carefully composing tensor, pipeline and data parallelism around the link hierarchy (Narayanan et al., 2021).

Open versus proprietary. An open standard published in April 2025 targets up to 1,024 accelerators in one domain at 200 Gb/s per lane. Buyers weigh lock-in against the maturity of established proprietary links (UALink Consortium, 2025).

Copper to light. As domains grow beyond a rack, links need optics, and vendors are moving optics into the switch package. One claims 3.5 times better power efficiency, a vendor figure not independently tested (NVIDIA, 2025).

Examples as of 2026-10-30

NVLink and NVLink Switch (NVIDIA)
UALink (open standard)
AMD Infinity Fabric
Google TPU inter-chip links with optical circuit switches

Sources

How it connects

GPUs & AI accelerators share work through Chip-to-chip interconnect.
Chip-to-chip interconnect joins chips into GPU clusters & orchestration.