# Fabs & the chip supply chain

URL: https://justuju.org/concept/chip-supply-chain/
Layer 1 · Physical & Energy

Advanced AI chips depend on a handful of highly specialised factories, tools and materials.

## D1 · Story

Chips are made in special factories called fabs, which are cleaner than a hospital. Only a few places in the world can make the most advanced chips.
It's like a recipe that needs a special oven that only a few bakeries own.
1. Design: drawing the chip
2. Make: in a super-clean factory (a fab)
3. Put together: add memory, then test
4. Data centre: the chip goes to work
Like: A special oven that only a few bakeries have.

## D2 · Picture

Making an AI accelerator involves chip design, fabrication at a foundry, advanced packaging that places memory right next to the processor, and testing.
Each step relies on specialised equipment and suppliers, and several steps are concentrated in a small number of companies and countries.
That concentration is why chip supply shows up in trade policy and export controls.
1. Design: chip architecture
2. Fabrication: at a foundry
3. Packaging: joins memory
4. Test: and assembly
5. Servers: into data centres
Like: Like a relay race where some legs can only be run by one or two athletes in the world. Where it breaks: In a relay a missing runner can be replaced by a slower one. In chip-making some steps have no practical substitute at all in the short term.

## D5 · Frontier

D2 draws chip-making as a pipeline. At the leading edge several stages have one or two suppliers, so the open questions are about concentration and policy as much as technology.
One lithography supplier. A single firm makes every EUV lithography machine, and it expects its next-generation High-NA tools to support volume manufacturing only from 2027 (ASML 20-F, 2026).
Geography. In 2022 almost all leading-edge (below 10 nm) logic capacity sat in Taiwan and South Korea. An industry study projects the US could make nearly 30% by 2032 if planned fabs are built (SIA and BCG, 2024).
The cost of spreading out. The largest foundry expects overseas fabs to cut its gross margin by 2 to 3 points at first and 3 to 4 points later, while calling its AI packaging capacity very tight (TSMC, Q3 2025 call).
Export controls. US rules in December 2024 extended controls to high-bandwidth memory and more chip-making tools. Whether controls slow rivals or speed up their home-grown substitutes is contested (BIS, 2024).

## Examples as of 2026-10-30

- TSMC (leading-edge foundry and CoWoS packaging)
- ASML (EUV lithography machines)
- SK hynix, Samsung and Micron (HBM memory)
- Intel Foundry and Samsung Foundry (other leading-edge fabs)

## Sources

- SIA & BCG: Emerging Resilience in the Semiconductor Supply Chain: https://www.semiconductors.org/wp-content/uploads/2024/05/Report_Emerging-Resilience-in-the-Semiconductor-Supply-Chain.pdf
- SIA & BCG: Strengthening the Global Semiconductor Supply Chain in an Uncertain Era: https://www.semiconductors.org/wp-content/uploads/2021/05/BCG-x-SIA-Strengthening-the-Global-Semiconductor-Value-Chain-April-2021_1.pdf
- ASML Form 20-F, fiscal year 2025: https://www.sec.gov/Archives/edgar/data/0000937966/000162828026011378/asml-20251231.htm
- BIS rule: Refinements to Controls for Advanced Computing and Semiconductor Manufacturing Items: https://www.govinfo.gov/content/pkg/FR-2024-12-05/pdf/2024-28270.pdf
- SemiAnalysis: AI Capacity Constraints - CoWoS and HBM Supply Chain: https://newsletter.semianalysis.com/p/ai-capacity-constraints-cowos-and
- TSMC Q3 2025 earnings call transcript: https://investor.tsmc.com/english/encrypt/files/encrypt_file/reports/2025-10/6860312f04fd291d0f26b46c1234f84e6332717e/TSMC%203Q25%20Transcript.pdf


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